Chip design for submicron VLSI:CMOS layout & simulation (Record no. 43348)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00351nam a2200121Ia 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 210219s9999||||xx |||||||||||||| ||und|| |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.38 |
| Item number | UY-C |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Uyemura,John P |
| 9 (RLIN) | 15205 |
| 245 #0 - TITLE STATEMENT | |
| Title | Chip design for submicron VLSI:CMOS layout & simulation |
| Statement of responsibility, etc. | John PUyemura |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | New Delhi |
| Name of publisher, distributor, etc. | Cengage Learning |
| Date of publication, distribution, etc. | 2006 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 411 |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Total checkouts | Barcode | Date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Central Library, NIT Jalandhar | Central Library, NIT Jalandhar | General Stacks | 20.02.2021 | 82098 | 20.02.2021 | 20.02.2021 | Books and Monographs | |||||
| Central Library, NIT Jalandhar | Central Library, NIT Jalandhar | General Stacks | 20.02.2021 | 82099 | 20.02.2021 | 20.02.2021 | Books and Monographs | |||||
| Central Library, NIT Jalandhar | Central Library, NIT Jalandhar | General Stacks | 20.02.2021 | 82100 | 20.02.2021 | 20.02.2021 | Books and Monographs | |||||
| Central Library, NIT Jalandhar | Central Library, NIT Jalandhar | General Stacks | 20.02.2021 | 82101 | 20.02.2021 | 20.02.2021 | Books and Monographs | |||||
| Central Library, NIT Jalandhar | Central Library, NIT Jalandhar | General Stacks | 20.02.2021 | 82102 | 20.02.2021 | 20.02.2021 | Books and Monographs |