| 000 | 00637nam a22001817a 4500 | ||
|---|---|---|---|
| 005 | 20230908121131.0 | ||
| 008 | 230908b |||||||| |||| 00| 0 eng d | ||
| 041 | _aeng | ||
| 082 | _a621 | ||
| 100 |
_aGUPTA, SURAJ _931048 |
||
| 245 | _aFPGA Implementation of Reed Solomon Decoder | ||
| 260 |
_bDepartment of Electronics and Communication Engineering Dr. B. R. Ambedkar National Institute of Technology TECHANo OF 144008, Punjab (India) _c2023 |
||
| 300 | _a71p | ||
| 502 | _aTHIS THESIS BELONGS TO DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING | ||
| 526 |
_aMTECH _b21204114 |
||
| 700 | _eAshish Raman | ||
| 942 | _cTH | ||
| 999 |
_c198604 _d198604 |
||